The present invention relates to an electromagnetic delay line which incorporates a coil and a capacitor, and in particular to a low profile high speed electromagnetic delay line which is suitable for transmission of super high speed signals having rise times less than about one nanosecond.
In the conventional art, an electromagnetic delay line in which coils and capacitors are connected in a ladder network is typically packaged as a dual-in-line package, and is mounted on a circuit board in the same manner as are ICs. Nowadays, a circuit board on which are mounted, for instance, high speed ECL (emitter coupled logic) circuits among other ICs, is typically made as an expensive multi layered circuit board composed of fluoride resin, for the purpose of reducing signal transmission losses. However, as the length of the wiring between the ECLs gets longer, the delay time for transmitting the signal increases, and this increases the timing errors between signals. Further, the cost rises. It is therefore desirable to reduce the wiring length on the circuit board by reducing the size of the circuit board, and to increase the mounting density of the electronic components thereon.
In view of such circumstances, it is desirable for an electromagnetic delay line to have a single-in-line package configuration (hereinafter abbreviated as SIP) which occupies a small mounting area.
However, an electromagnetic delay line which is suitable for super high speed signals and has a low profile while being in SIP form is hard to produce with high productivity, due to its cumbersomeness in manufacture, and special arrangement is required for the configuration of the coils and the capacitors. As a result, as yet no SIP type super high speed electromagnetic delay line has yet been put into commercial production.